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LP61L1008 Series
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Document Title 128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM Revision History
Rev. No.
2.0
History
Add Product Family and 32-pin sTSOP (Type I) package
Issue Date
June 11, 2002
Remark
(June, 2002, Version 2.0)
AMIC Technology, Inc.
LP61L1008 Series
128K X 8 BIT 3.3V HIGH SPEED CENTER POWER CMOS SRAM
Features
n Single 3.3V 10% power supply n Access times: 12/15 ns (max.) n Current: Operating: 180mA (max.) Standby: 5mA (max.) n Full static operation, no clock or refreshing required n All inputs and outputs are directly TTL compatible n Center Power/Ground Pin Configuration n Common I/O using three-state output n Output enable and two chip enable inputs for easy application n Data retention voltage: 2.0V (min.) n Available in 32-pin SOJ 300 mil and 32-pin sTSOP packages
General Description The LP61L1008 is a high speed 1,048,576-bit static random access memory organized as 131,072 words by 8 bits and operates on a single 3.3V power supply.
Inputs and three-state outputs are TTL compatible and allow for direct interfacing with common system bus structures. The chip enable input is provided for POWER-DOWN and device enable and an output enable input is included for easy interfacing. Data retention is guaranteed at a power supply voltage as low as 2.0V.
Product Family Product Family
LP61L1008 Operating Temperature 0C~70C VCC Range 3.0V~3.6V
Power Dissipation Speed
12/15 ns Data Retention (ICCDR, Typ.) 10A Standby (ISB1, Typ.) 20A Operating (ICC2, Typ.) 66mA
Package Type 32L SOJ 32L sTSOP
1. Typical values are measured at VCC = 3.0V, TA = 25C and not 100% tested. 2. Data retention current VCC = 2.0V.
Pin Configuration n SOJ
A0 A1 A2 A3 CE I/O1 I/O2 VCC GND I/O3 I/O4 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 A16 A0 A1 A2 A3 CE I/O0 I/O1 VCC VSS I/O2 I/O3 WE A4 A5 A6 A7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
n sTSOP
~
A15 A14 A13 OE I/O8 I/O7 GND VCC I/O6 I/O5 A12 A11 A10 A9 A8
LP61L1008X
~ ~
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
A16 A15 A14 A13 OE I/O7 I/O6 VSS VCC I/O5 I/O4 A12 A11 A10 A9 A8
LP61L1008S
(June, 2002, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Block Diagram
A0
VCC GND 256 X 4096 DECODER MEMORY ARRAY
A14 A15 A16
I/O1 INPUT DATA CIRCUIT I/O8 COLUMN I/O
CE OE WE
CONTROL CIRCUIT
Pin Description
Pin No. 1 - 4, 13 - 21, 29- 32 12 28 5 6 -7, 10 - 11, 22 - 23, 26 - 27 8, 24 9, 25 Symbol A0 - A16 Description Address Inputs
WE OE CE I/O1 - I/O8
Write Enable Output Enable Chip Enable Data Input/Outputs
VCC GND
Power Supply Ground
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Recommended DC Operating Conditions
(TA = 0C to + 70C) Symbol VCC GND VIH VIL CL TTL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Output Load Output Load Min. 3.0 0 2.2 -0.3 Typ. 3.3 0 0 Max. 3.6 0 VCC + 0.3 +0.8 30 1 Unit V V V V pF -
Absolute Maximum Ratings*
VCC to GND .............................................. -0.5V to +4.6V IN, IN/OUT Volt to GND .....................-0.5V to VCC +0.5V Operating Temperature, Topr ...................... 0C to +70C Storage Temperature, Tstg..................... -55C to +125C Temperature Under Bias, Tbias................ -10C to +85C Power Dissipation, Pt................................................1.0W Soldering Temp. & Time .............................260C, 10 sec
*Comments
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
DC Electrical Characteristics
Symbol ILI ILO
(TA = 0C to + 70C, VCC = 3.3V 10%, GND = 0V) LP61L1008-12/15 Unit Min. Max. 2 A A VIN = GND to VCC CE = VIH or Conditions
Parameter Input Leakage Current
Output Leakage Current -12 -15
-
2 180 170 20 5 0.4 -
OE = VIH or WE = VIL VI/O = GND to VCC CE = VIL II/O = 0 mA CE = VIH CE VCC - 0.2V, VIN 0.2V or VIN VCC - 0.2V IOL = 8 mA IOH = -4 mA
ICC1 (1) ISB ISB1 VOL VOH
Dynamic Operating Current
mA mA mA V V
Standby Power Supply Current Output Low Voltage Output High Voltage
2.4
Note: 1. ICC1 is dependent on output loading, cycle rates, and Read / Write patterns.
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Truth Table
Mode Standby Output Disable Read Write Note: X = H or L CE H L L L OE X H L X WE X H H L I/O Operation High Z High Z DOUT DIN Supply Current ISB, ISB1 ICC1 ICC1 ICC1
Capacitance (TA = 25C, f = 1.0MHz)
Symbol CIN* CI/O* Parameter Input Capacitance Input/Output Capacitance Min. Max. 8 10 Unit pF pF Conditions VIN = 0V VI/O = 0V
* These parameters are sampled and not 100% tested.
AC Characteristics (TA = 0C to +70C, VCC = 3.3V 10%, GND = 0V)
Symbol Parameter LP61L1008-12 Min. Read Cycle tRC tAA tACE tOE tCLZ tOLZ tCHZ tOHZ tOH Read Cycle Time Address Access Time Chip Enable Access Time Output Enable to Output Valid Chip Enable to Output in Low Z Output Enable to Output in Low Z Chip Disable to Output in High Z Output Disable to Output in High Z Output Hold from Address Change CE CE CE 12 3 2 2 2 12 12 7 7 7 15 5 2 2 5 15 15 9 10 9 ns ns ns ns ns ns ns ns ns Max. LP61L1008-15 Min. Max. Unit
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
AC Characteristics (continued)
Symbol Parameter LP61L1008-12 Min. Write Cycle tWC tCW tAS tAW tWP tWR tWHZ tDW tDH tOW Write Cycle Time Chip Enable to End of Write Address Setup Time of Write Address Valid to End of Write Write Pulse Width Write Recovery Time Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 12 10 0 10 8 0 0 8 0 5 7 15 12 0 12 10 0 0 10 0 5 8 ns ns ns ns ns ns ns ns ns ns Max. LP61L1008-15 Min. Max. Unit
Notes: tCHZ1, tCHZ2, tOHZ, and tWHZ are defined as the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels.
Timing Waveforms
Read Cycle 1
(1, 2, 4)
tRC Address
tAA tOH tOH
DOUT
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Read Cycle 2
(1, 3, 4, 6)
CE
tACE tCLZ5
tCHZ5
DOUT
Read Cycle 3
(1)
tRC Address
tAA
OE
tOE tOLZ5 CE
tOH
tACE tCHZ5
DOUT
Notes: 1. WE is high for Read Cycle. 2. Device is continuously enabled CE = VI. 3. Address valid prior to or coincident with CE transition low. 4. OE = VIL. 5. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Timing Waveforms (continued)
Write Cycle 1 (Write Enable Controlled)
tWC Address tAW tCW5 CE (4) tWR3 (6)
tAS1
tWP2
WE
tDW DIN tWHZ
tDH
tOW DOUT
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Timing Waveforms (continued)
Write Cycle 2 (Chip Enable Controlled)
tWC Address tAW tCW5 CE tAS1 (4) tWR3
tCW5 tWP2 WE
tDW DIN
tDH
tWHZ7
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write. 2. A Write occurs during the overlap (tWP) of a low CE and a low WE . 3. tWR is measured from the earliest of CE or WE going high to the end of the Write cycle. 4. If the CE low transition with the WE low transition or after the WE transition, outputs remain in a high impedance state. 5. tCW is measured from the later of CE going low to the end of Write. 6. OE is continuously low. ( OE = VIL) 7. Transition is measured 500mV from steady state. This parameter is sampled and not 100% tested.
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
AC Test Conditions
Input Pulse Levels Input Rise and Fall Time Input and Output Timing Reference Levels Output Load 0V to 3.0V 3 ns 1.5V See Figures 1 and 2
+3.3V 320 Output ZO=50 RL=50 VT=1.5V 350 5pF* I/O
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for tCLZ, tOHZ, tOLZ, tCHZ, tWHZ, and tOW
Data Retention Characteristics (TA = 0C to 70C)
Symbol Parameter Min. Max. Unit Conditions CE VCC - 0.2V VCC = 3.0V ICCDR1 Data Retention Current 5 mA CE VCC - 0.2V VIN VCC - 0.2V or VIN 0.2V
VDR1
VCC for Data Retention
2
3.6
V
tCDR
Chip Disable to Data Retention Time
0
-
ns See Retention Waveform
tR
Operation Recovery Time
5
-
ms
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Low VCC Data Retention Waveform ( CE Controlled)
DATA RETENTION MODE VCC 3.0V tCDR VDR 2V 3.0V tR
CE
VIH CE VDR - 0.2V
VIH
Ordering Information
Part No. LP61L1008S-12 LP61L1008X-12 LP61L1008S-15 LP61L1008X-15 Access Time (ns) 12 12 15 15 Operating Current Max. (mA) 180 180 170 170 Standby Current Max. (mA) 5 5 5 5 Package 32L SOJ (300 mil) 32L sTSOP (Type I) 32L SOJ (300 mil) 32L sTSOP (Type I)
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
LP61L1008 Series
Package Information SOJ 32/32LD (300mil BODY) Outline Dimensions
D 32 17 b
unit: inches/mm
F F DETAIL "A" BASE METAL WITH PLATING SECTION F-F
1
16
E
DETAIL "A" HE b1 A2
A
s SEATING PLANE
b
e
MIN 0.026"
y
y e1 0.004 y
Symbol A A1 A2 b b1 c D HE E e1 e s y
Dimensions in inches Min. 0128 0.052 0.095 0.016 0.026 0.006 0.820 0.330 0.295 0.260 Nom. 0.132 0.100 0.018 0.028 0.008 0.825 0.335 0.300 0.267 0.050 Max. 0.140 0.105 0.020 0.032 0.012 0.830 0.340 0.305 0.274 0.048 0.004
D
A1
Dimensions in mm Min. 3.25 2.08 2.41 0.41 0.66 0.15 20.83 8.39 7.49 6.61 Nom. 3.35 2.54 0.46 0.71 0.20 20.96 8.51 7.62 6.78 1.27 Max. 3.56 2.67 0.51 0.81 0.30 21.08 8.63 7.75 6.96 1.22 0.10
Notes: 1. The maximum value of dimension D includes end flash. 2. Dimension E doesn't include resin fins. 3. Dimension e1 is for PC Board surface mount pad pitch design reference only. 4. Dimension S includes end flash.
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
c
LP61L1008 Series
Package Information sTSOP 32L TYPE I (8 X 13.4mm) Outline Dimensions
unit: inches/mm
e
A2
E
A1
c
L LE Detail "A"
D1 D Detail "A"
D
0.076MM
S
SEATING PLANE
b
Dimensions in inches Symbol A A1 A2 b c E e D D1 L LE S 0 0.520 0.461 0.012 0.0275 Min 0.002 0.037 0.007 0.0056 0.311 Nom 0.039 0.008 0.0059 0.315 0.020 TYP 0.528 0.465 0.020 0.0315 0.0109 TYP 3 5 0.535 0.469 0.028 0.0355 Max 0.049 0.041 0.009 0.0062 0.319
Dimensions in mm Min 0.05 0.95 0.17 0.142 7.90 Nom 1.00 0.20 0.150 8.00 0.50 TYP 13.20 11.70 0.30 0.700 13.40 11.80 0.50 0.800 0.278 TYP 0 3 5 13.60 11.90 0.70 0.900 Max 1.25 1.05 0.23 0.158 8.10
Notes: 1. The maximum value of dimension D1 includes end flash. 2. Dimension E does not include resin fins. 3. Dimension S includes end flash.
(June, 2001, Version 2.0)
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AMIC Technology, Inc.
A

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